Electronic appliances including televisions, refrigerators and so on are operated with external commercial AC (Alternating Current) power. Electronic apparatuses including laptop computers, mobile terminals, PDAs (Personal Digital Assistants) and so on are also operated with commercial AC power and their internal batteries may be charged with commercial AC power. Such electronic appliances and electronic apparatuses (hereinafter collectively referred to as electronic apparatuses) contain a power supply (inverter or an AC/DC converter) for converting commercial AC power into DC (Direct Current) power or an inverter is incorporated in an external power adapter (AC adapter) of the electronic apparatuses.
FIG. 1 is a circuit diagram showing a basic configuration of an inverter 100r. The inverter 100r includes, as main parts, a fuse 102, an input capacitor Ci, a filter 104, a diode rectifier circuit 106, a smoothing capacitor Cs and an isolated DC/DC converter 110r. 
A commercial AC voltage VAC is input to the filter 104 via the fuse 102 and the input capacitor Ci. The filter 104 removes noise from the commercial AC voltage VAC. The diode rectifier circuit 106 is a diode bridge circuit for full-wave rectification of the commercial AC voltage VAC. An output voltage of the diode rectifier circuit 106 is smoothed by the smoothing capacitor Cs and is then converted into a DC voltage VIN.
The DC/DC converter (flyback converter) 110r receives and steps down the DC voltage VIN at an input terminal P1 and supplies an output voltage VOUT stabilized to a target value to a load (not shown) connected to an output terminal P2.
The DC/DC converter 110r includes a control circuit 2r, a switching transistor M1, an output circuit 200 and a feedback circuit 210. The output circuit 200 includes a transformer T1, a first diode D1, a first output capacitor Co1, a detection resistor RS, a second diode D2 and a second output capacitor Co2. The topology of the output circuit 200 is typical and therefore, explanation thereof will be omitted.
By the switching operation of the switching transistor M1, the input voltage VIN is dropped and the output voltage VOUT is generated. In addition, by adjusting a duty cycle of the switching operation of the switching transistor M1, the control circuit 2r controls a coil current Ip flowing into a primary winding W1 of the transformer T1 while stabilizing the output voltage VOUT to the target value.
The detection resistor RS is connected in series to the primary winding W1 of the transformer T1 and the switching transistor M1. A voltage drop (detection voltage) VCS proportional to the current Ip flowing into the primary winding W1 and the switching transistor M1 is produced in the detection resistor RS. The control circuit 2r controls the current Ip flowing into the primary winding W1 on the basis of the detection voltage VCS.
The feedback circuit 210 generates a feedback voltage VFB depending on the output voltage VOUT and supplies it to a feedback terminal (FB terminal) of the control circuit 2r. The feedback circuit 210 includes a shunt regulator 212 and a photo coupler 214. The shunt regulator 212 generates a feedback signal S11 having a level regulated such that an error between the output voltage VOUT and a predetermined target value becomes zero, and supplies the generated feedback signal S11 to a light emitting diode of the photo coupler 214. A photo transistor of the photo coupler 214 converts a light signal S12 emitted from the light emitting diode into the feedback voltage VFB depending on the feedback signal S11.
The primary side of the transformer T1 has an auxiliary winding W3 in addition to the primary winding W1. The auxiliary winding W3, the second diode D2 and the second output capacitor Co2 form a second DC/DC converter. In response to the switching operation of the switching transistor M1, a DC voltage VCC is produced in the second output capacitor Co2. The DC voltage VCC is supplied to a power terminal VCC (VCC terminal) of the control circuit 2r. 
The control circuit 2r generates a pulse signal (switching output) SOUT alternating between an ON level corresponding to switch-ON of the switching transistor M1 and an OFF level corresponding to switch-OFF of the switching transistor M1. Then, the control circuit 2r supplies the switching output SOUT to a gate of the switching transistor M1. When a duty cycle of the switching output SOUT is adjusted, the output voltage VOUT is stabilized to a target value.
FIG. 2 is a circuit diagram showing a configuration of the control circuit 2r. The control circuit 2r includes a pulse modulator 10, a driver 20, a blanking circuit 40, a burst control circuit 50 and a voltage divider 80. The voltage divider 80 divides the feedback voltage VFB with a predetermined division ratio (for example, ¼). This division ratio is determined to supply sufficient power to a load (not shown) under heavy load conditions.
The blanking circuit 40 is provided to remove noise from the detection voltage VCS. Specifically, immediately after the switching transistor M1 is switched on, the detection signal VCS is masked during a predetermined blanking interval. The blanking circuit 40 may be omitted.
The pulse modulator 10 generates a pulse signal SPWM based on a detection voltage VCS′ outputted from the blanking circuit 40 and a feedback voltage VFB′ outputted from the voltage divider 80. The pulse modulator 10 includes an oscillator 12, a comparator 14 and a SR flip-flop 16. The oscillator 12 generates a set signal SSET asserted (having a high level) with a predetermined cycle and inputs the set signal SSET to a set terminal S of the SR flip-flop 16. When the detection voltage VCS′ reaches a lower one of the feedback voltage VFB′ and a predetermined upper limit voltage VLIM1 in an ON period of the switching transistor M1, the comparator 14 asserts (having a high level) a reset signal SRESET and outputs the asserted reset signal SRESET to a rest terminal R of the flip-flop 16. The pulse signal SPWM outputted from the SR flip-flop 16 transitions to an ON level of the switching transistor M1 whenever the set signal SSET is asserted, and transitions to an OFF level whenever the reset signal SRESET is asserted.
The driver 20 switches the switching transistor M1 based on the pulse signal SPWM.
Under light load conditions, the DC/DC converter 110 causes the switching transistor M1 to perform an intermittent operation (burst operation) in order to increase efficiency by reducing power consumption. Specifically, the DC/DC converter M1 alternates between a switching period during which the switching transistor M1 is operated and a stop period during which the switching transistor M1 remains in an OFF condition.
The burst control circuit 50 is provided to detect the light load conditions of the DC/DC converter 110 and control the burst operation. Under the light load conditions where a load connected to the output terminal P2 is light, i.e., an output current is small, the output voltage VOUT is increased and the feedback voltage VFB is decreased. The burst control circuit 50 compares the feedback voltage VFB with a predetermined first burst threshold VBURST1 and asserts (for example, having a high level) a light load detection signal S_BURST if the feedback voltage VFB is decreased to the first burst threshold VBURST1. In addition, when the light load detection signal S_BURST is asserted, the burst control circuit 50 negates (for example, having a low level) the light load detection signal S_BURST if the feedback voltage VFB reaches a second burst threshold VBURST2. While the light load detection signal S_BURST1 is being asserted, the pulse modulator 10 fixes the pulse signal SPWM to an OFF level and stops the switching operation of the switching transistor M1.
FIG. 3 is a view showing a relationship between the feedback voltage VFB and the peak value VCS_PEAK of the detection voltage VCS in the control circuit 2r. In the control circuit 2r of FIG. 2, the feedback voltage VFB′ (corresponding to ¼ of VFB) outputted from the voltage divider 80 is compared with the detection voltage VCS. Accordingly, the peak value of the detection voltage VCS becomes equal to ¼ of the feedback voltage VFB. Regardless of the level of the feedback voltage VFB, the peak value VCS_PEAK of the detection voltage VCS is clamped at the upper limit voltage VLIM1 and, accordingly, the coil current Ip is limited to an upper limit current ILIM1 depending on the upper limit voltage VLIM1.
FIG. 4 is a waveform diagram showing an operation of the DC/DC converter 110r under the light load conditions. A period from time A to time B represents a switching period of the switching transistor M1. When the switching output SOUT has a high level, the switching transistor M1 is switched on. When the switching transistor M1 is switched on, the current Ip begins to flow into the switching transistor M1 and the primary winding W1. The current Ip is increased with a certain slope with time, and accordingly, the detection voltage VCS is increased. During this period, energy is stored in the transformer T1. Then, when the coil current Ip reaches its peak value depending on the feedback voltage VFB, the switching transistor M1 is switched off.
When the switching transistor M1 is switched off, a charging current flows through the secondary winding W2 of the transformer T1 and the diode D1, the output capacitor Co1 is charged, and the output voltage VOUT is increased. The energy stored in the transformer T1 is released by this charging current. This operation is repeated in the switching period A-B.
When the output voltage VOUT is increased in the switching period A-B, the feedback voltage VFB is decreased. Then, when the feedback voltage VFB is decreased to the first burst threshold VBURST1, a stop period arrives. When the feedback voltage VFB reaches the second burst threshold VBURST2 at time C, a switching time arrives and the switching operation of the switching transistor M1 resumes. FIG. 4 shows a case where VBURST1=VBURST2.
The present inventor has reviewed the DC/DC converter 110r and recognized the following problems. In the light load mode, the feedback voltage VFB and the detection voltage VCS shuttle within a range indicated by an arrow in FIG. 3. As described above, the division ratio of the voltage divider 80 is determined under the presumption of heavy load conditions. As a result, the peak value of the detection voltage VCS in the light load conditions, i.e., the peak value of the current Ip flowing into the switching transistor M1, is excessively increased. If the current Ip immediately after the DC/DC converter 110r transitions from the stop period to the switching period when the burst operation is increased, a variation of the magnetic flux density of the transformer T1 is increased to produce a ringing sound from the transformer T1.
In addition, if the peak value of the current Ip flowing into the switching transistor M1 is increased, there rises a problem of increased energy stored in the transformer T1 per cycle of the switching operation and an increase in the width of a ripple of the output voltage VOUT during the burst operation.
These problems and mechanisms causing the problems should not be regarded as a general awareness of those skilled in the art but should be considered to be uniquely recognize present inventor.